Oxide reliability is the study of device lifetime, modes of failure, and these effects on device operation. The study of metal oxide semiconductor (MOS) device breakdown begins with the gate oxide material. The gate dielectric is the most fragile element of a transistor because it is an extremely thin layer of material biased during normal operation. Scaling of the gate oxide thickness, tox, causes the oxide to be more susceptible to gate current leakage, defect creation, and ultimately dielectric breakdown. The oxide reliability team uses state of the art semiconductor characterization equipment to assess the reliability of the gate dielectric in cutting edge semiconductor devices, from both silicon dioxide (SiO2) and high-k (e.g. HfO2) material systems. We are particularly interested in the effects of dielectric breakdown on the DC and AC performance of simple complementary MOS (CMOS) logic circuits, such as inverters and NAND gates.
As device dimensions in conventional MOSFET devices continue to decrease, the gate leakage current through the SiO2 gate oxide has reached unacceptably high levels. To continue to reduce device dimensions and increase device performance, alternative dielectric materials to SiO2 based dielectrics are being used as replacement. Alternative gate dielectrics can require interfacial layers which complicate understanding device reliability and testing. The high-k project group designs tests to probe defects in the high-k dielectric and interfacial layer and assess their impact on the gate dielectric integrity.
To aid in understanding MOS structures with multiple dielectrics, the high-k group has developed a program to assist in visualizing the energy band diagrams. Techniques commonly employed to understand high-k dielectrics include:
- Gate leakage current tests
- Family of curves
- Threshold voltage
- Sub-threshold slope measurements
- Charge pumping
- Capacitance-voltage tests
- Fast pulse measurements
To better predict and approximate high-k electrical characteristics, our research group has developed the Band Diagram Program, capable of generating energy band diagrams for complex MOS structures. Useful features of this program include:
- Ability to simulate complex MOS stacks with multiple dielectric layers.
- Generation of an energy band diagram for the MOS structure
- Electrical characteristic predictions including C-V curves
- Simulation of device breakdown via definable interface traps and fixed charges.
This program is available for free download here.
Simple IC Building Blocks
Reliability of devices (nMOSFETs, pMOSFETs, MOSCAPs, etc) and products (CPUs, Graphics Processors, DRAMs, ASICs, etc) are very different. Product reliability can be significantly longer then that predicted by device reliability. Breakdown in a single device can be non-catastrophic in a circuit. The reliability of simple integrated circuit (IC) building blocks, that larger circuits are composed of, investigates the reliability of simple circuits like:
- NAND gate
- NOR gate
By understanding the reliability of simple IC building blocks better reliability predications can be made about the product reliability.
- Ryan Thompson (ECE, Winter Break 2008)
- Shem Purnell (ECE, Winter Break 2009)
- Blake Rapp (ECE, Spring 2010)
- Shane Pugmire (ECE, Winter Break 2010)
- Dr. Gennadi Bersuker & Dr. Rino Choi (SEMATECH)
- Prof. Tibor Grasser (Technische Universität Wien, Austria)
- Dr. Ben Kaczer (Inter-University Microelectronics Center-IMEC, Leuven, Belgium)
- Prof. L. Larcher and Dr. A. Padovani (Università di Modena e Reggio Emilia, Modène, Italy)
- Prof. A.J. Moll (Boise State)
- Prof. R. Jacob (Jake) Baker (Boise State): supported by 2001 DoD Multidisciplinary University Research Initiative (MURI) with the University of Maryland
- Multidisciplinary University Research Initiative (MURI) with the University of Maryland
- Dr. Amr Haggag (Freescale Semiconductor)
- Dr. Du Li (Micron Technology)
- Santosh Kumar (Novolem, Inc. – formerly Cypress Semiconductor)
- 2008 Idaho SBoE Small HERC Grant
- NASA Idaho Space Grant Consortium
- Cypress Semiconductor
- 2002 Boise State University Faculty Research Program
- 2003 Micron Campus Engineering Research Program (undergraduate summer research)
- 2004 NASA Idaho EPSCoR Program
- 2004 NIH INBRE
- DARPA project
- 2001 Multidisciplinary University Research Initiative (MURI) with the University of Maryland
- Idaho NSF EPSCoR
- 2002 NSF MRI Grant